Various semiconductor integrated circuits include devices that are formed with layers of dielectric or insulating material. These dielectric/insulating layers are used as stress controlling films, barrier layers, liner layers, and capping layers, for example, for nano-devices and structures, which are fabricated using front end of line (FEOL) and back end of the line (BEOL) processes. As feature sizes and line rules become increasingly smaller, it becomes increasingly necessary to implement thinner dielectric and insulating layers with lower dielectric constants, higher voltage break down strengths, and improved leakage characteristics. Moreover, as dielectric and insulating layers are made increasingly thinner for certain applications, these dielectric and insulating layers must be able to withstand damage due to subsequent processing steps, such as damage or loss due to plasma exposures (e.g., reactive ion etch (RIE), strip, dielectric barrier etch), chemical mechanical polishing (CMP) and wet cleans (e.g., post RIE dilute hydrofluoric (DHF) cleans).